PCEdev Wiki
nesdev_db
https://pce.nesdev.org/wiki/PCEdev_Wiki
MediaWiki 1.39.0
first-letter
Media
Special
Talk
User
User talk
Pce wiki
Pce wiki talk
File
File talk
MediaWiki
MediaWiki talk
Template
Template talk
Help
Help talk
Category
Category talk
PCEdev Wiki
0
1
1
2023-04-01T06:18:36Z
Fiskbit
37
Main page skeleton so there's something.
wikitext
text/x-wiki
'''PC-Engine Development Wiki'''
== Reference ==
f8845396cba9e5171876693aac94440e751e3d10
13
1
2023-08-16T07:53:48Z
Fiskbit
37
Adds pinout links.
wikitext
text/x-wiki
'''PC-Engine Development Wiki'''
== Reference ==
===Pinouts===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
80a7b5a1ac4c4a9a04972978c7d40e63b6ffbc4f
14
13
2023-08-16T07:54:16Z
Fiskbit
37
Adds wiki name.
wikitext
text/x-wiki
'''PCEdev: PC-Engine Development Wiki'''
== Reference ==
===Pinouts===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
534831e53146e3aacbb0ac7de70787def302fb50
15
14
2023-08-23T09:18:22Z
Fiskbit
37
Fiskbit moved page [[Main Page]] to [[PCEdev Wiki]]: Rename main page to match wiki name.
wikitext
text/x-wiki
'''PCEdev: PC-Engine Development Wiki'''
== Reference ==
===Pinouts===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
534831e53146e3aacbb0ac7de70787def302fb50
18
15
2023-08-23T09:19:00Z
Fiskbit
37
Remove redundant statement of the wiki name.
wikitext
text/x-wiki
'''PC-Engine Development Wiki'''
== Reference ==
===Pinouts===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
80a7b5a1ac4c4a9a04972978c7d40e63b6ffbc4f
22
18
2023-08-28T13:25:36Z
Fiskbit
37
No dash in PC Engine.
wikitext
text/x-wiki
'''PC Engine Development Wiki'''
== Reference ==
===Pinouts===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
1616237cac67738a9b2fe2c5aad303d24c95e524
26
22
2023-08-28T13:35:20Z
Fiskbit
37
Creates General section. Adds CPU addresses and CPU memory map pages to it.
wikitext
text/x-wiki
'''PC Engine Development Wiki'''
== Reference ==
=== General ===
* [[CPU addresses]]
* [[CPU memory map]]
=== Pinouts ===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
68c7706fb52892719dd864fc6978e06d55f7b375
27
26
2023-08-28T13:38:41Z
Fiskbit
37
Adds MediaWiki links.
wikitext
text/x-wiki
'''PC Engine Development Wiki'''
== Reference ==
=== General ===
* [[CPU addresses]]
* [[CPU memory map]]
=== Pinouts ===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
== MediaWiki ==
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]
d732b47e8b558bf87b926f43316ce152fc8cd916
33
27
2023-08-28T15:40:58Z
Asie
351
/* General */ add Timing
wikitext
text/x-wiki
'''PC Engine Development Wiki'''
== Reference ==
=== General ===
* [[CPU addresses]]
* [[CPU memory map]]
* [[Timing]]
=== Pinouts ===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
== MediaWiki ==
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]
a1f6d3ec1c8b6e2ed6ad6e7e6bfe473ffcf8f2bf
35
33
2023-08-28T15:48:11Z
Asie
351
/* Reference */ add general system outline
wikitext
text/x-wiki
'''PC Engine Development Wiki'''
== Reference ==
=== General ===
* [[CPU addresses]]
* [[CPU memory map]]
* [[Timing]]
=== Components ===
* PC Engine
** [[CPU]] (HuC6280)
*** [[Timer]]
*** [[Joypad]]
*** [[Interrupts]]
*** [[PSG]] (Programmable Sound Generator)
** [[VDC]] (Video Display Controller, HuC6270)
** [[VCE]] (Video Color Encoder, HuC6260)
** [[VPC]] (Video Priority Controller; SuperGrafx only)
* [[PC Engine CD]]
** [[PC Engine CD BIOS]]
=== HuCards ===
* [[Street Fighter 2 mapper]]
* [[Super System Card]]
* [[Arcade Card]]
=== Pinouts ===
* [[CPU pinout]]
* [[VDC pinout]]
* [[HuCard pinout]]
== MediaWiki ==
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]
af8c77f29999a8a7a15c46e4aabae59f7472dfb1
37
35
2023-08-29T09:16:34Z
Fiskbit
37
Adds VCE pinout.
wikitext
text/x-wiki
'''PC Engine Development Wiki'''
== Reference ==
=== General ===
* [[CPU addresses]]
* [[CPU memory map]]
* [[Timing]]
=== Components ===
* PC Engine
** [[CPU]] (HuC6280)
*** [[Timer]]
*** [[Joypad]]
*** [[Interrupts]]
*** [[PSG]] (Programmable Sound Generator)
** [[VDC]] (Video Display Controller, HuC6270)
** [[VCE]] (Video Color Encoder, HuC6260)
** [[VPC]] (Video Priority Controller; SuperGrafx only)
* [[PC Engine CD]]
** [[PC Engine CD BIOS]]
=== HuCards ===
* [[Street Fighter 2 mapper]]
* [[Super System Card]]
* [[Arcade Card]]
=== Pinouts ===
* [[CPU pinout]]
* [[VDC pinout]]
* [[VCE pinout]]
* [[HuCard pinout]]
== MediaWiki ==
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Help:Contents User's Guide]
* [https://www.mediawiki.org/wiki/Special:MyLanguage/Manual:FAQ MediaWiki FAQ]
* [[:Category:Deletion requests|Deletion requests]]
4ad51532a9e2cbd6fc766245e1f1aed8525bf073
MediaWiki:Loginprompt
8
2
2
2023-04-01T06:44:08Z
Fiskbit
37
Adds log-in prompt explaining how to register an account.
wikitext
text/x-wiki
Looking to register an account? Because of spam, accounts are currently created manually by request. Please reach out to Fiskbit or lidnariq on the [http://forums.nesdev.org/ NESdev forums] or [https://discord.gg/JSG4kuF8EK NESdev Discord server] if you'd like to contribute to the wiki.
250f3ff9f50ef5476c10ce328ab8981594ebfd68
MediaWiki:Common.css
8
3
3
2023-04-01T06:49:09Z
Brizzo
1
Created page with "/* CSS placed here will be applied to all skins */ pre,.mw-code { white-space:pre; overflow-x: auto; }"
css
text/css
/* CSS placed here will be applied to all skins */
pre,.mw-code { white-space:pre; overflow-x: auto; }
adf7543e1d65a87e58e60fb01ec9e4e2d7f4afaa
5
3
2023-05-27T05:35:22Z
Brizzo
1
css
text/css
/* CSS placed here will be applied to all skins */
/* If a table is actually a table, you can add attractive borders
and dark gray TH by changing the first line to
{| class="tabular"
*/
table.tabular {
margin: 1em 1em 1em 0; background: #f9f9f9; border: 1px solid #aaa; border-collapse: collapse
}
table.tabular th, table.tabular td {
border: 1px solid #aaaaaa; padding: 0.2em
}
table.tabular th {
background: #f2f2f2; text-align: center
}
table.tabular caption {
margin-left: inherit; margin-right: inherit
}
table.oddf0 tr:nth-of-type(odd) {
background: #F0F0F0;
}
table.evenf0 tr:nth-of-type(even) {
background: #F0F0F0;
}
/*
* Below taken directly from:
* http://www.mediawiki.org/wiki/MediaWiki:Common.css
*/
/*
This is the CSS for all skins (for all users) on MediaWiki.org.
SECTIONS:
1. Indication of namespaces
2. Color classes for content
3. Special pages
4. Main page styling
5. Sidebar external links
6. Extension:Matrix stuff
7. Wikitables, infobox templates, warnings, and other such stylings
8. Some other small things
*/
/** 1. INDICATION OF NAMESPACES **/
/* Pseudo NS Special (light grey) */
.ns--2 #content { background-color: #f4f4f4; }
.ns--2 div.thumb { border-color: #f4f4f4; }
/* NS Project + Project_talk (light sky blue) */
.ns-4 #content, .ns-5 #content { background-color: #f8fcff; }
.ns-4 div.thumb, .ns-5 div.thumb { border-color: #f8fcff; }
/* NS MediaWiki + MediaWiki_talk (light grey) */
.ns-8 #content, .ns-9 #content { background-color: #f4f4f4; }
.ns-8 div.thumb, .ns-9 div.thumb { border-color: #f4f4f4; }
/* NS Manual + Manual_talk (light bluish violet) */
.ns-100 #content, .ns-101 #content { background-color: #f3f3ff; }
.ns-100 div.thumb, .ns-101 div.thumb { border-color: #f3f3ff; }
/* NS Help (but NOT Help_talk) (blue border and Public Domain icon) */
.ns-12 #content {
border: 2px solid #0000cc;
border-right: none;
background-image: url(http://upload.wikimedia.org/wikipedia/mediawiki/b/b8/PD-banner.png);
background-repeat: no-repeat;
background-position: right top;
}
.ns-12 #bodyContent {
background-image: url(http://upload.wikimedia.org/wikipedia/mediawiki/6/67/PD-icon-faded.png);
background-repeat: no-repeat;
background-position: right 5em;
}
/***** 2. COLOR CLASSES FOR CONTENT *****/
/* Border colors */
.borderc1 { border-color: #e9e9e9; border-width: thin; }
.borderc2 { border-color: #aaaaaa; border-width: thin; }
.borderc3 { border-color: #777777; border-width: thin; }
.borderc4 { border-color: #000000; border-width: thin; }
.borderc5 { border-color: #c00000; border-width: thin; }
.borderc6 { border-color: #025e9d; border-width: thin; }
.borderc7 { border-color: #008040; border-width: thin; }
.borderc8 { border-color: #ffcc00; border-width: thin; } /* Used by: [[Template:Welcome]]. */
/* Background colors */
.backgroundc1 { background-color: #ffffff; } /* Used by: [[Template:Welcome]]. */
.backgroundc2 { background-color: #f9f9f9; }
.backgroundc3 { background-color: #eeeeee; }
.backgroundc4 { background-color: #e0e0e0; }
.backgroundc5 { background-color: #d2d2d2; }
.backgroundc6 { background-color: #b7b7b7; }
.backgroundc7 { background-color: #a3a3a3; }
.backgroundc8 { background-color: #444455; }
/** 3. SPECIAL PAGES **/
/* Consistent special page navigation */
.SpecialPageInfo {
background-color: #f9f9f9;
background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/8/89/Exquisite-khelpcenter.png/35px-Exquisite-khelpcenter.png);
background-position: 0.8em 0.5em;
background-repeat: no-repeat;
padding: 0.3em 0.5em 0.3em 5.0em;
border-color: #025e9d;
border-width: 1px;
border-style: solid;
border-bottom-width: medium;
margin-bottom: 1em;
}
.mw-viewprevnext {
display: block;
border: 1px solid #cccccc;
background-color: #f9f9f2;
padding: 0.2em 0.4em;
}
/** 4. MAIN PAGE STYLING **/
#mainpage_topbox {
background: #f9f9f9;
padding: 0px;
border: 1px solid #aaaaaa;
margin: 0.2em 10px 10px;
}
.mainpage_boxtitle, .mainpage_hubtitle, #mainpage_pagetitle {
font-size: 105%;
padding: 0.4em;
background-color: #eeeeee;
border-bottom: 1px solid #aaaaaa;
}
.mainpage_boxtitle {
line-height: 120%;
}
#mainpage_pagetitle {
color: #cf7606;
font-size: 200% !important;
}
#mainpage_sitelinks {
padding: 0.2em;
text-align: center;
background-color: white;
}
.mainpage_hubtitle {
text-align: center;
}
.mainpage_boxcontents, .mainpage_boxcontents_small {
background: #ffffff;
padding: 0.2em 0.4em;
}
.mainpage_boxcontents_small {
font-size: 95%;
}
.mainpage_hubbox, #mainpage_newscell, #mainpage_downloadcell {
padding: 0;
border: 1px solid #aaaaaa;
}
.mainpage_hubbox {
margin-bottom: 0;
}
#mainpage_newscell {
margin-bottom: 15px;
margin-top: 0 !important;
}
#mainpage_newscell .mainpage_boxtitle {
background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/8/89/Exquisite-khelpcenter.png/20px-Exquisite-khelpcenter.png);
background-repeat: no-repeat;
background-position: 99% 0.3em;
padding-right: 25px;
}
#mainpage_downloadcell {
width: 17em;
margin-bottom: 5px;
}
#mainpage_downloadcell .mainpage_boxtitle {
background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/5/5d/Crystal_Clear_action_build.png/18px-Crystal_Clear_action_build.png);
background-repeat: no-repeat;
background-position: 96% 0.33em;
padding-right: 25px;
}
#mainpage_mwtitle { color: #005288; } /* The words 'MediaWiki.org' in the title. */
/* The "mainpage" class is added to the body with JavaScript for the main page in all */
/* languages, so we can style things that apppear on the main page and also elsewhere. */
.mainpage #lastmod,
.mainpage #siteSub,
.mainpage h1.firstHeading {
display: none !important;
}
.mainpage #content {
padding-top: 1em;
}
/** 5. SIDEBAR EXTERNAL LINKS **/
#n-blog-text a, #n-browse-svn a, #n-Statistics-for-SVN a, #n-phpdoc a, #n-svn-statistics a {
background: url(/skins-1.5/monobook/external.png) center right no-repeat;
padding-right: 13px;
color: #3366bb;
}
/** 7. WIKITABLES, INFOBOX TEMPLATES, WARNINGS AND OTHER SUCH STYLINGS **/
/* Give wikitables blue headings */
.wikitable th, .wikitable td.hl3, .wikitable th.hl3 {
background: #8da7d6;
}
.wikitable td.hl1, .wikitable th.hl1 {
background: #c5d8fc;
}
.wikitable td.hl2, .wikitable th.hl2 {
background: #a7c1f2;
}
/**
* Make entire table valign=top,
* To replace the |valign=top| on every cell.
*/
.vatop tr, tr.vatop, .vatop td, .vatop th {
vertical-align: top;
}
/* General purpose "pretty (data) tables" */
table.datatable {
background-color: transparent;
}
table.datatable th, table.datatable td {
padding: 4px;
}
table.datatable th {
text-align: left;
background-color: #999999;
}
table.datatable tr {
background-color: #cccccc;
}
table.datatable tr:hover {
background-color: #ffffcc;
}
/* SideBox styling */
div.sideBox {
position: relative;
float: right;
background: white;
margin-left: 1em;
border: 1px solid gray;
padding: 0.3em;
width: 200px;
overflow: hidden;
clear: right;
}
div.sideBox dl {
padding: 0;
margin: 0 0 0.3em 0;
font-size: 96%;
}
div.sideBox dl dt {
background: none;
margin: 0.4em 0 0 0;
}
div.sideBox dl dd {
margin: 0.1em 0 0 1.1em;
background-color: #f3f3f3;
}
/* Extension infobox styling */
.ext-infobox {
border: 2px solid #aaaaaa;
width: 272px;
float: right;
margin: 0 0 0.5em 0.5em;
border-collapse: collapse;
background-color: white;
}
.ext-infobox td {
border: 2px none #aaaaaa;
padding: 0.2em 0.5em;
border-bottom: 1px solid #f0f0f0 !important;
}
.ext-header {
background-color: #aaaaaa;
color: white;
text-align: left;
}
.ext-header td { padding-top: 0.5em; }
.ext-header img { padding: 0 0.2em 0 0.5em; }
.ext-status-unstable, .ext-status-unstable td { border-color: #990000; }
.ext-status-unstable .ext-header { background-color: #990000; color: #ffff00; }
.ext-status-experimental, .ext-status-experimental td { border-color: #ff4500; }
.ext-status-experimental .ext-header { background-color: #ff4500; }
.ext-status-beta, .ext-status-beta td { border-color: #ffba01; }
.ext-status-beta .ext-header { background-color: #ffba01; }
.ext-status-stable, .ext-status-stable td { border-color: #32cd32; }
.ext-status-stable .ext-header { background-color: #32cd32; }
/* Version box on [[Manual:Downloading MediaWiki]] */
#DownloadVersionBox {
border: 2px solid black;
border-collapse: collapse;
margin: auto;
width: 50%;
color: black;
}
#DownloadVersionBox td {
border: 2px solid black;
padding: 20px;
}
/* Major warning - used on the main page template to warn against editing carelessly, but can be used elsewhere as well */
.majorwarning {
background: yellow;
padding: 0.3em;
text-align: center;
font-size: 125%;
border: 2px solid red;
}
/* Page headings used throughout the wiki (though not very much at the time of writing…) */
.page-notice, .page-warning {
border-width: 1px;
border-style: solid;
padding: 0.3em 0.5em;
margin-bottom: 1em;
width: 95%;
margin-left: auto;
margin-right: auto;
text-align: center;
}
/* Informative notices at the top of pages (blue) */
.page-notice {
background-color: #f9f9f9;
border-color: #025e9d;
text-align: left;
}
/* Warning information at the top of pages (red) */
.page-warning {
background-color: #ffffff;
border-color: #c51919;
border-width: 2px;
}
.pw-head {
color: #c51919;
font-weight: bold;
}
/* Used in Template:Notice */
.block-note {
background-image: url(http://upload.wikimedia.org/wikipedia/commons/thumb/6/60/Bulbgraph.png/18px-Bulbgraph.png);
background-position: top left;
background-repeat: no-repeat;
}
/*
Using block-contents in the hope that it can apply to all block-level warning templates,
with different images applied as backgrounds to the wrapping DIV.
*/
.block-contents {
display: block;
padding-left: 20px;
}
/* Template documentation ([[Template:Documentation]]) */
.template-documentation {
clear: both;
margin: 1em 0 0 0;
border: 1px solid #aaa;
background-color: #ecfcf4;
padding: 5px;
}
/** 8. SOME OTHER SMALL THINGS **/
/* Give a bit of space to the TOC */
#toc { margin: 1em 0; }
/* Allow limiting of which header levels are shown in a TOC;
<div class="toclimit-3">, for instance, will limit to
showing ==headings== and ===headings=== but no further.
Used in [[Template:TOCright]]
*/
.toclimit-2 .toclevel-1 ul,
.toclimit-3 .toclevel-2 ul,
.toclimit-4 .toclevel-3 ul,
.toclimit-5 .toclevel-4 ul,
.toclimit-6 .toclevel-5 ul,
.toclimit-7 .toclevel-6 ul {
display: none;
}
/* make the list of references look smaller and highlight clicked reference in blue */
ol.references { font-size: 100%; }
.references-small { font-size: 90%; }
ol.references > li:target { background-color: #ddeeff; }
sup.reference:target { background-color: #ddeeff; }
/* extra buttons for edit dialog (from commons:MediaWiki:Common.css) */
.my-buttons {
padding: .5em;
}
.my-buttons a {
color: black;
background-color: #cde !important;
font-weight: bold;
font-size: .9em;
text-decoration: none;
border: thin #069 outset;
padding: 0 .1em .1em;
}
.my-buttons a:hover, .my-buttons a:active {
background-color: #bcd;
border-style: inset;
}
/* from [[User:Splarka/Help:Linked images]] */
.imagelink_wikilogo a {
width: 135px;
height: 135px;
display: block;
text-decoration: none;
background-image: url("http://upload.wikimedia.org/wikipedia/mediawiki/b/bc/Wiki.png");
}
/** reduced subset of the mbox styles from enwiki, mainly for the nice boxflow **/
table.mbox {
margin: 4px 10%;
border-collapse: collapse;
border: 1px solid #aaa; /* Default "notice" gray */
background: #f9f9f9;
}
table.mbox-wide {
margin: 4px 0;
}
th.mbox-text, td.mbox-text { /* The message body cell(s) */
border: none;
padding: 0.25em 0.9em; /* 0.9em left/right */
width: 100%; /* Make all mboxes the same width regardless of text length */
}
td.mbox-image { /* The left image cell */
border: none;
padding: 2px 0 2px 0.9em; /* 0.9em left, 0px right */
text-align: center;
}
td.mbox-imageright { /* The right image cell */
border: none;
padding: 2px 0.9em 2px 0; /* 0px left, 0.9em right */
text-align: center;
}
td.mbox-empty-cell { /* An empty narrow cell */
border: none;
padding: 0px;
width: 1px;
}
/* These mbox-small classes must be placed after all other
ambox/tmbox/ombox etc classes. "body.mediawiki" is so
they override "table.ambox + table.ambox" above. */
body.mediawiki table.mbox-small { /* For the "small=yes" option. */
clear: right;
float: right;
margin: 4px 0 4px 1em;
width: 238px;
font-size: 88%;
line-height: 1.25em;
}
body.mediawiki table.mbox-small-left { /* For the "small=left" option. */
margin: 4px 1em 4px 0;
width: 238px;
border-collapse: collapse;
font-size: 88%;
line-height: 1.25em;
}
/* These are the same colours as the enwiki
'cmbox' styles; just with different names. */
table.mbox-critical {
border: 4px solid #b22222; /* Red */
background: #FFDBDB; /* Pink */
}
table.mbox-important {
background: #FFDBDB; /* Red */
}
table.mbox-warning {
background: #FFE7CE; /* Orange */
}
table.mbox-caution {
background: #FFF9DB; /* Yellow */
}
table.mbox-notice {
background: #D8E8FF; /* Blue */
}
table.mbox-move {
background: #E4D8FF; /* Purple */
}
table.mbox-protection {
background: #EFEFE1; /* Gray-gold */
}
/**
* Infoboxes
*/
.infobox {
float: right;
clear: right;
margin-bottom: 0.5em;
margin-left: 1em;
padding: 0.2em;
border: 1px solid #AAA;
background: #F9F9F9;
color: black;
}
.infobox td,
.infobox th {
vertical-align: top;
}
.infobox caption {
margin-left: inherit;
font-size: larger;
}
.infobox.bordered {
border-collapse: collapse;
}
.infobox.bordered td,
.infobox.bordered th {
border: 1px solid #AAA;
}
.infobox.bordered .borderless td,
.infobox.bordered .borderless th {
border: 0;
}
/* Apparently the namespaces parameter
for inputbox forces a checkbox.
Let's hide it in the API sidebar */
.mw-inputbox-hideapicheck label[for=mw-inputbox-ns104],
#mw-inputbox-ns104 {
display: none;
}
/** Testing for code review **/
div.mw-wordcloud {
width: 100%;
text-align: justify;
}
.mw-wordcloud-size-1 {
color: #222;
font-size: 2.4em;
}
.mw-wordcloud-size-2 {
color: #333;
font-size:2.2em;
}
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font-style: italic;
margin-bottom: 0.5em;
padding-left: 2em;
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/* @todo FIXME: document me :) */
#signuptopbox li {
float: left;
list-style: none;
font-family: sans-serif;
}
#signuptopbox li {
color: #3ca7d4;
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border-color: #fff #fff #fff #67ca36;
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7b014c1d6648715d37f0e5bdbc8085bd023638be
MediaWiki:Sidebar
8
4
4
2023-04-01T06:59:21Z
Fiskbit
37
Updates the sidebar.
wikitext
text/x-wiki
* navigation
** mainpage|Wiki main page
** http://forums.nesdev.org/ | NESdev Forums
** https://discord.gg/JSG4kuF8EK | NESdev Discord
** recentchanges-url|recentchanges
* SEARCH
* TOOLBOX
* LANGUAGES
d3889c8a1c188f221c689d5bb4dca061db57ed59
CPU pinout
0
5
6
2023-08-16T07:31:39Z
Fiskbit
37
Adds CPU pinout.
wikitext
text/x-wiki
CPU pinout
==Pinout==
^
/ \
/ \
/ \
CPU PA5 <- / 1 80 \ -> CPU PA6
CPU PA4 <- / 2 79 \ -> CPU PA7
CPU PA3 <- / 3 78 \ -> CPU PA8
CPU PA2 <- / 4 O 77 \ -> CPU PA9
CPU PA1 <- / 5 76 \ -- +5V (VBB)
CPU PA0 <- / 6 75 \ -- GND (VSS2)
GND (VSS1) -- / 7 74 \ -> CPU PA10
+5V (VAA) -- / 8 73 \ -> CPU PA11
n/c ?? / 9 72 \ -> CPU PA12
OSC -> / 10 71 \ -> CPU PA13
/RST -> / 11 70 \ -> CPU PA14
RDY -> / 12 69 \ -> CPU PA15
SX <- / 13 68 \ -> CPU PA16
HSM <- / 14 67 \ -> CPU PA17
+5V (VPPD) -- / 15 66 \ -> CPU PA18
GND (VSS5) -- / 16 65 \ -> CPU PA19
AUDIO LOUT <- / 17 \
AUDIO ROUT <- / 18 /
+5V AUDIO (VPPA) -- / 19 64 / -> CPU PA20
GND AUDIO (AGND) -- / 20 63 / -> CPU /WR
GND (VSSA) -- / 21 HuC6280 HUDSON 62 / -> CPU /RD
K0 -> / 22 Package QFP-80 61 / -> /CER
n/c ?? / 23 60 / -> /CE7
K1 -> / 24 59 / -> /CEK
/ 58 / -- GND (VSS3)
\ 57 / -- +5V (VCC)
K2 -> \ 25 56 / <> CPU D7
K3 -> \ 26 55 / <> CPU D6 Orientation:
K4 -> \ 27 54 / <> CPU D5 --------------------
K5 -> \ 28 53 / <> CPU D4 64 41
K6 -> \ 29 52 / <> CPU D3 | |
K7 -> \ 30 51 / <> CPU D2 .-----------.
O0 <- \ 31 50 / <> CPU D1 65-| O|-40
O1 <- \ 32 49 / <> CPU D0 | HuC6280|
O2 <- \ 33 48 / -- GND (VSS4) 80-|O HUDSON |-25
O3 <- \ 34 47 / -- +5V (VDD) '-----------'
O4 <- \ 35 46 / -> SYNC | |
O5 <- \ 36 45 / <- /NMI 01 24
O6 <- \ 37 O 44 / <- /IRQ1
O7 <- \ 38 43 / <- /IRQ2 Legend:
/EAT -> \ 39 42 / <- /EA1 ----------------------------
/EA3 -> \ 40 41 / <- /EA2 --[HuC6280]-- Power, n/a
\ / ->[HuC6280]<- HuC6280 input
\ / <-[HuC6280]-> HuC6280 output
\ / <>[HuC6280]<> Bidirectional
V ??[HuC6280]?? Unknown
==Signal descriptions==
* '''OSC''': 21.4772 MHz clock input.
* '''SX''': An inverted output of the system clock, normally not connected.
* '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13.
* '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read.
* '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write.0
* '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB.
* '''CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF
* '''CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF
* '''EAT''', '''EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus).
* '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode.
* '''/IRQ1''': Interrupt input from the VDC.
* '''/IRQ2''': Interrupt input from HuCards and the expansion port.
* '''/NMI''': Non-maskable input from the expansion port.
* '''SYNC''': Asserted during opcode fetch and deasserted otherwise (including during reset). Can be used for single-stepping execution, but is normally not connected.
* '''RDY''': Ready. Deasserting halts the CPU until asserted again.
* '''/RST''': Reset.
2a177d09cb25f69efeebedcbda614b2b937c132f
7
6
2023-08-16T07:31:57Z
Fiskbit
37
Remove unnecessary header.
wikitext
text/x-wiki
==Pinout==
^
/ \
/ \
/ \
CPU PA5 <- / 1 80 \ -> CPU PA6
CPU PA4 <- / 2 79 \ -> CPU PA7
CPU PA3 <- / 3 78 \ -> CPU PA8
CPU PA2 <- / 4 O 77 \ -> CPU PA9
CPU PA1 <- / 5 76 \ -- +5V (VBB)
CPU PA0 <- / 6 75 \ -- GND (VSS2)
GND (VSS1) -- / 7 74 \ -> CPU PA10
+5V (VAA) -- / 8 73 \ -> CPU PA11
n/c ?? / 9 72 \ -> CPU PA12
OSC -> / 10 71 \ -> CPU PA13
/RST -> / 11 70 \ -> CPU PA14
RDY -> / 12 69 \ -> CPU PA15
SX <- / 13 68 \ -> CPU PA16
HSM <- / 14 67 \ -> CPU PA17
+5V (VPPD) -- / 15 66 \ -> CPU PA18
GND (VSS5) -- / 16 65 \ -> CPU PA19
AUDIO LOUT <- / 17 \
AUDIO ROUT <- / 18 /
+5V AUDIO (VPPA) -- / 19 64 / -> CPU PA20
GND AUDIO (AGND) -- / 20 63 / -> CPU /WR
GND (VSSA) -- / 21 HuC6280 HUDSON 62 / -> CPU /RD
K0 -> / 22 Package QFP-80 61 / -> /CER
n/c ?? / 23 60 / -> /CE7
K1 -> / 24 59 / -> /CEK
/ 58 / -- GND (VSS3)
\ 57 / -- +5V (VCC)
K2 -> \ 25 56 / <> CPU D7
K3 -> \ 26 55 / <> CPU D6 Orientation:
K4 -> \ 27 54 / <> CPU D5 --------------------
K5 -> \ 28 53 / <> CPU D4 64 41
K6 -> \ 29 52 / <> CPU D3 | |
K7 -> \ 30 51 / <> CPU D2 .-----------.
O0 <- \ 31 50 / <> CPU D1 65-| O|-40
O1 <- \ 32 49 / <> CPU D0 | HuC6280|
O2 <- \ 33 48 / -- GND (VSS4) 80-|O HUDSON |-25
O3 <- \ 34 47 / -- +5V (VDD) '-----------'
O4 <- \ 35 46 / -> SYNC | |
O5 <- \ 36 45 / <- /NMI 01 24
O6 <- \ 37 O 44 / <- /IRQ1
O7 <- \ 38 43 / <- /IRQ2 Legend:
/EAT -> \ 39 42 / <- /EA1 ----------------------------
/EA3 -> \ 40 41 / <- /EA2 --[HuC6280]-- Power, n/a
\ / ->[HuC6280]<- HuC6280 input
\ / <-[HuC6280]-> HuC6280 output
\ / <>[HuC6280]<> Bidirectional
V ??[HuC6280]?? Unknown
==Signal descriptions==
* '''OSC''': 21.4772 MHz clock input.
* '''SX''': An inverted output of the system clock, normally not connected.
* '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13.
* '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read.
* '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write.0
* '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB.
* '''CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF
* '''CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF
* '''EAT''', '''EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus).
* '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode.
* '''/IRQ1''': Interrupt input from the VDC.
* '''/IRQ2''': Interrupt input from HuCards and the expansion port.
* '''/NMI''': Non-maskable input from the expansion port.
* '''SYNC''': Asserted during opcode fetch and deasserted otherwise (including during reset). Can be used for single-stepping execution, but is normally not connected.
* '''RDY''': Ready. Deasserting halts the CPU until asserted again.
* '''/RST''': Reset.
5902c10dc3163a4d86710b04bcbf467f795d0ff4
12
7
2023-08-16T07:52:35Z
Fiskbit
37
Removes padding.
wikitext
text/x-wiki
==Pinout==
^
/ \
/ \
/ \
CPU PA5 <- / 1 80 \ -> CPU PA6
CPU PA4 <- / 2 79 \ -> CPU PA7
CPU PA3 <- / 3 78 \ -> CPU PA8
CPU PA2 <- / 4 O 77 \ -> CPU PA9
CPU PA1 <- / 5 76 \ -- +5V (VBB)
CPU PA0 <- / 6 75 \ -- GND (VSS2)
GND (VSS1) -- / 7 74 \ -> CPU PA10
+5V (VAA) -- / 8 73 \ -> CPU PA11
n/c ?? / 9 72 \ -> CPU PA12
OSC -> / 10 71 \ -> CPU PA13
/RST -> / 11 70 \ -> CPU PA14
RDY -> / 12 69 \ -> CPU PA15
SX <- / 13 68 \ -> CPU PA16
HSM <- / 14 67 \ -> CPU PA17
+5V (VPPD) -- / 15 66 \ -> CPU PA18
GND (VSS5) -- / 16 65 \ -> CPU PA19
AUDIO LOUT <- / 17 \
AUDIO ROUT <- / 18 /
+5V AUDIO (VPPA) -- / 19 64 / -> CPU PA20
GND AUDIO (AGND) -- / 20 63 / -> CPU /WR
GND (VSSA) -- / 21 HuC6280 HUDSON 62 / -> CPU /RD
K0 -> / 22 Package QFP-80 61 / -> /CER
n/c ?? / 23 60 / -> /CE7
K1 -> / 24 59 / -> /CEK
/ 58 / -- GND (VSS3)
\ 57 / -- +5V (VCC)
K2 -> \ 25 56 / <> CPU D7
K3 -> \ 26 55 / <> CPU D6 Orientation:
K4 -> \ 27 54 / <> CPU D5 --------------------
K5 -> \ 28 53 / <> CPU D4 64 41
K6 -> \ 29 52 / <> CPU D3 | |
K7 -> \ 30 51 / <> CPU D2 .-----------.
O0 <- \ 31 50 / <> CPU D1 65-| O|-40
O1 <- \ 32 49 / <> CPU D0 | HuC6280|
O2 <- \ 33 48 / -- GND (VSS4) 80-|O HUDSON |-25
O3 <- \ 34 47 / -- +5V (VDD) '-----------'
O4 <- \ 35 46 / -> SYNC | |
O5 <- \ 36 45 / <- /NMI 01 24
O6 <- \ 37 O 44 / <- /IRQ1
O7 <- \ 38 43 / <- /IRQ2 Legend:
/EAT -> \ 39 42 / <- /EA1 ----------------------------
/EA3 -> \ 40 41 / <- /EA2 --[HuC6280]-- Power, n/a
\ / ->[HuC6280]<- HuC6280 input
\ / <-[HuC6280]-> HuC6280 output
\ / <>[HuC6280]<> Bidirectional
V ??[HuC6280]?? Unknown
==Signal descriptions==
* '''OSC''': 21.4772 MHz clock input.
* '''SX''': An inverted output of the system clock, normally not connected.
* '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13.
* '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read.
* '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write.0
* '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB.
* '''CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF
* '''CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF
* '''EAT''', '''EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus).
* '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode.
* '''/IRQ1''': Interrupt input from the VDC.
* '''/IRQ2''': Interrupt input from HuCards and the expansion port.
* '''/NMI''': Non-maskable input from the expansion port.
* '''SYNC''': Asserted during opcode fetch and deasserted otherwise (including during reset). Can be used for single-stepping execution, but is normally not connected.
* '''RDY''': Ready. Deasserting halts the CPU until asserted again.
* '''/RST''': Reset.
100a7c5cec4017159399b7b9f1b2a0aef74fd269
19
12
2023-08-28T01:26:00Z
Lidnariq
7
/* Signal descriptions */ edito
wikitext
text/x-wiki
==Pinout==
^
/ \
/ \
/ \
CPU PA5 <- / 1 80 \ -> CPU PA6
CPU PA4 <- / 2 79 \ -> CPU PA7
CPU PA3 <- / 3 78 \ -> CPU PA8
CPU PA2 <- / 4 O 77 \ -> CPU PA9
CPU PA1 <- / 5 76 \ -- +5V (VBB)
CPU PA0 <- / 6 75 \ -- GND (VSS2)
GND (VSS1) -- / 7 74 \ -> CPU PA10
+5V (VAA) -- / 8 73 \ -> CPU PA11
n/c ?? / 9 72 \ -> CPU PA12
OSC -> / 10 71 \ -> CPU PA13
/RST -> / 11 70 \ -> CPU PA14
RDY -> / 12 69 \ -> CPU PA15
SX <- / 13 68 \ -> CPU PA16
HSM <- / 14 67 \ -> CPU PA17
+5V (VPPD) -- / 15 66 \ -> CPU PA18
GND (VSS5) -- / 16 65 \ -> CPU PA19
AUDIO LOUT <- / 17 \
AUDIO ROUT <- / 18 /
+5V AUDIO (VPPA) -- / 19 64 / -> CPU PA20
GND AUDIO (AGND) -- / 20 63 / -> CPU /WR
GND (VSSA) -- / 21 HuC6280 HUDSON 62 / -> CPU /RD
K0 -> / 22 Package QFP-80 61 / -> /CER
n/c ?? / 23 60 / -> /CE7
K1 -> / 24 59 / -> /CEK
/ 58 / -- GND (VSS3)
\ 57 / -- +5V (VCC)
K2 -> \ 25 56 / <> CPU D7
K3 -> \ 26 55 / <> CPU D6 Orientation:
K4 -> \ 27 54 / <> CPU D5 --------------------
K5 -> \ 28 53 / <> CPU D4 64 41
K6 -> \ 29 52 / <> CPU D3 | |
K7 -> \ 30 51 / <> CPU D2 .-----------.
O0 <- \ 31 50 / <> CPU D1 65-| O|-40
O1 <- \ 32 49 / <> CPU D0 | HuC6280|
O2 <- \ 33 48 / -- GND (VSS4) 80-|O HUDSON |-25
O3 <- \ 34 47 / -- +5V (VDD) '-----------'
O4 <- \ 35 46 / -> SYNC | |
O5 <- \ 36 45 / <- /NMI 01 24
O6 <- \ 37 O 44 / <- /IRQ1
O7 <- \ 38 43 / <- /IRQ2 Legend:
/EAT -> \ 39 42 / <- /EA1 ----------------------------
/EA3 -> \ 40 41 / <- /EA2 --[HuC6280]-- Power, n/a
\ / ->[HuC6280]<- HuC6280 input
\ / <-[HuC6280]-> HuC6280 output
\ / <>[HuC6280]<> Bidirectional
V ??[HuC6280]?? Unknown
==Signal descriptions==
* '''OSC''': 21.4772 MHz clock input.
* '''SX''': An inverted output of the system clock, normally not connected.
* '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13.
* '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read.
* '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write.
* '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB.
* '''CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF
* '''CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF
* '''EAT''', '''EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus).
* '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode.
* '''/IRQ1''': Interrupt input from the VDC.
* '''/IRQ2''': Interrupt input from HuCards and the expansion port.
* '''/NMI''': Non-maskable input from the expansion port.
* '''SYNC''': Asserted during opcode fetch and deasserted otherwise (including during reset). Can be used for single-stepping execution, but is normally not connected.
* '''RDY''': Ready. Deasserting halts the CPU until asserted again.
* '''/RST''': Reset.
5f0324300780bc864b7558bb5802cc0f2bc338d6
20
19
2023-08-28T07:21:51Z
Fiskbit
37
/* Signal descriptions */ Fixes active-low pins that were listed in as active-high.
wikitext
text/x-wiki
==Pinout==
^
/ \
/ \
/ \
CPU PA5 <- / 1 80 \ -> CPU PA6
CPU PA4 <- / 2 79 \ -> CPU PA7
CPU PA3 <- / 3 78 \ -> CPU PA8
CPU PA2 <- / 4 O 77 \ -> CPU PA9
CPU PA1 <- / 5 76 \ -- +5V (VBB)
CPU PA0 <- / 6 75 \ -- GND (VSS2)
GND (VSS1) -- / 7 74 \ -> CPU PA10
+5V (VAA) -- / 8 73 \ -> CPU PA11
n/c ?? / 9 72 \ -> CPU PA12
OSC -> / 10 71 \ -> CPU PA13
/RST -> / 11 70 \ -> CPU PA14
RDY -> / 12 69 \ -> CPU PA15
SX <- / 13 68 \ -> CPU PA16
HSM <- / 14 67 \ -> CPU PA17
+5V (VPPD) -- / 15 66 \ -> CPU PA18
GND (VSS5) -- / 16 65 \ -> CPU PA19
AUDIO LOUT <- / 17 \
AUDIO ROUT <- / 18 /
+5V AUDIO (VPPA) -- / 19 64 / -> CPU PA20
GND AUDIO (AGND) -- / 20 63 / -> CPU /WR
GND (VSSA) -- / 21 HuC6280 HUDSON 62 / -> CPU /RD
K0 -> / 22 Package QFP-80 61 / -> /CER
n/c ?? / 23 60 / -> /CE7
K1 -> / 24 59 / -> /CEK
/ 58 / -- GND (VSS3)
\ 57 / -- +5V (VCC)
K2 -> \ 25 56 / <> CPU D7
K3 -> \ 26 55 / <> CPU D6 Orientation:
K4 -> \ 27 54 / <> CPU D5 --------------------
K5 -> \ 28 53 / <> CPU D4 64 41
K6 -> \ 29 52 / <> CPU D3 | |
K7 -> \ 30 51 / <> CPU D2 .-----------.
O0 <- \ 31 50 / <> CPU D1 65-| O|-40
O1 <- \ 32 49 / <> CPU D0 | HuC6280|
O2 <- \ 33 48 / -- GND (VSS4) 80-|O HUDSON |-25
O3 <- \ 34 47 / -- +5V (VDD) '-----------'
O4 <- \ 35 46 / -> SYNC | |
O5 <- \ 36 45 / <- /NMI 01 24
O6 <- \ 37 O 44 / <- /IRQ1
O7 <- \ 38 43 / <- /IRQ2 Legend:
/EAT -> \ 39 42 / <- /EA1 ----------------------------
/EA3 -> \ 40 41 / <- /EA2 --[HuC6280]-- Power, n/a
\ / ->[HuC6280]<- HuC6280 input
\ / <-[HuC6280]-> HuC6280 output
\ / <>[HuC6280]<> Bidirectional
V ??[HuC6280]?? Unknown
==Signal descriptions==
* '''OSC''': 21.4772 MHz clock input.
* '''SX''': An inverted output of the system clock, normally not connected.
* '''CPU PA20..0''': CPU physical address. PA12..0 come from the 65C02 core's A12..0 and PA20..13 from the MMU, selected by the 65C02 core's A15..13.
* '''K7..0''': General-purpose input (GPI) mapped to $FF:$1000-$13FF read.
* '''O7..0''': General-purpose output (GPO) mapped to $FF:$1000-$13FF write.
* '''/CER''': RAM chip enable. Asserted when accessing banks $F8-$FB.
* '''/CE7''': HuC6270 chip enable. Asserted when accessing $FF:$0000-$03FF
* '''/CEK''': HuC6260 chip enable. Asserted when accessing $FF:$0400-$07FF
* '''/EAT''', '''/EAT3..1''': CPU test inputs. EAT is a timer for the U-bus (HuC6280 internal peripheral bus).
* '''HSM''': High speed mode. Asserted if the CPU is running in its 7.16 MHz mode.
* '''/IRQ1''': Interrupt input from the VDC.
* '''/IRQ2''': Interrupt input from HuCards and the expansion port.
* '''/NMI''': Non-maskable input from the expansion port.
* '''SYNC''': Asserted during opcode fetch and deasserted otherwise (including during reset). Can be used for single-stepping execution, but is normally not connected.
* '''RDY''': Ready. Deasserting halts the CPU until asserted again.
* '''/RST''': Reset.
85c296e00952c7c7e950e5f8e7ddfc49320843c8
HuCard pinout
0
6
8
2023-08-16T07:40:21Z
Fiskbit
37
Adds HuCard pinout.
wikitext
text/x-wiki
==Pinout==
Card | | PC-Engine
-----+--+--------------------------
1 |->| /CD
2 |->| AUDIO IN
3 |<-| CPU PA19
4 |<-| CPU PA16
5 |<-| CPU PA15
6 |<-| CPU PA12
7 |<-| CPU PA7
8 |<-| CPU PA6
9 |<-| CPU PA5
10 |<-| CPU PA4
11 |<-| CPU PA3
12 |<-| CPU PA2
13 |<-| CPU PA1
14 |<-| CPU PA0
15 |<>| CPU D0 (PCE) or D7 (TG16)
16 |<>| CPU D1 (PCE) or D6 (TG16)
17 |<>| CPU D2 (PCE) or D5 (TG16)
18 |--| GND
19 |<>| CPU D3 (PCE) or D4 (TG16)
20 |<>| CPU D4 (PCE) or D3 (TG16)
21 |<>| CPU D5 (PCE) or D2 (TG16)
22 |<>| CPU D6 (PCE) or D1 (TG16) Orientation:
23 |<>| CPU D7 (PCE) or D0 (TG16) --------------------------
24 |<-| CPU PA20 .-------------------.
25 |<-| CPU PA10 | .---------..------|
26 |<-| CPU /RD | | || |- 1
27 |<-| CPU PA11 |>| Label || |
28 |<-| CPU PA9 | | || |- 38
29 |<-| CPU PA8 | '---------<nowiki>''</nowiki>------|
30 |<-| CPU PA13 '-------------------'
31 |<-| CPU PA14
32 |<-| CPU PA17 Legend:
33 |<-| CPU PA18 --------------------------
34 |<-| CPU /WR [HuCard]-- Power, n/a
35 |<-| HSM [HuCard]<- HuCard input
36 |<-| /RST [HuCard]-> HuCard output
37 |->| /IRQ2 [HuCard]<> Bidirectional
38 |--| +5V [HuCard]?? Unknown
==Signal descriptions==
* '''/CD''': Card detect. Connects to the expansion port. Grounded by the HuCard so the CD-ROM<sup>2</sup> can tell a card is inserted.
* '''AUDIO IN''': Mono audio. Mixed into both channels.
* '''CPU PA20..0''': CPU physical address (the 21-bit post-MMU address). PA20 is used as /CE.
* '''CPU D7..0''': The order of these pins depends on region. For PC-Engine, they are ascending, and for TurboGrafx-16, they are descending.
* '''HSM''': High speed mode, asserted by the CPU when operating at 7.16 MHz.
60a63da24c350072bdaefa2679d45edaff401d28
10
8
2023-08-16T07:51:46Z
Fiskbit
37
Removes ?? from legend because it's not present.
wikitext
text/x-wiki
==Pinout==
Card | | PC-Engine
-----+--+--------------------------
1 |->| /CD
2 |->| AUDIO IN
3 |<-| CPU PA19
4 |<-| CPU PA16
5 |<-| CPU PA15
6 |<-| CPU PA12
7 |<-| CPU PA7
8 |<-| CPU PA6
9 |<-| CPU PA5
10 |<-| CPU PA4
11 |<-| CPU PA3
12 |<-| CPU PA2
13 |<-| CPU PA1
14 |<-| CPU PA0
15 |<>| CPU D0 (PCE) or D7 (TG16)
16 |<>| CPU D1 (PCE) or D6 (TG16)
17 |<>| CPU D2 (PCE) or D5 (TG16)
18 |--| GND
19 |<>| CPU D3 (PCE) or D4 (TG16)
20 |<>| CPU D4 (PCE) or D3 (TG16)
21 |<>| CPU D5 (PCE) or D2 (TG16)
22 |<>| CPU D6 (PCE) or D1 (TG16)
23 |<>| CPU D7 (PCE) or D0 (TG16) Orientation:
24 |<-| CPU PA20 --------------------------
25 |<-| CPU PA10 .-------------------.
26 |<-| CPU /RD | .---------..------|
27 |<-| CPU PA11 | | || |- 1
28 |<-| CPU PA9 |>| Label || |
29 |<-| CPU PA8 | | || |- 38
30 |<-| CPU PA13 | '---------<nowiki>''</nowiki>------|
31 |<-| CPU PA14 '-------------------'
32 |<-| CPU PA17
33 |<-| CPU PA18 Legend:
34 |<-| CPU /WR --------------------------
35 |<-| HSM [HuCard]-- Power, n/a
36 |<-| /RST [HuCard]<- HuCard input
37 |->| /IRQ2 [HuCard]-> HuCard output
38 |--| +5V [HuCard]<> Bidirectional
==Signal descriptions==
* '''/CD''': Card detect. Connects to the expansion port. Grounded by the HuCard so the CD-ROM<sup>2</sup> can tell a card is inserted.
* '''AUDIO IN''': Mono audio. Mixed into both channels.
* '''CPU PA20..0''': CPU physical address (the 21-bit post-MMU address). PA20 is used as /CE.
* '''CPU D7..0''': The order of these pins depends on region. For PC-Engine, they are ascending, and for TurboGrafx-16, they are descending.
* '''HSM''': High speed mode, asserted by the CPU when operating at 7.16 MHz.
298a4ba63c5a5fe25290d7c46af9c0f7a58ff1ae
11
10
2023-08-16T07:52:07Z
Fiskbit
37
Removes padding.
wikitext
text/x-wiki
==Pinout==
Card | | PC-Engine
-----+--+--------------------------
1 |->| /CD
2 |->| AUDIO IN
3 |<-| CPU PA19
4 |<-| CPU PA16
5 |<-| CPU PA15
6 |<-| CPU PA12
7 |<-| CPU PA7
8 |<-| CPU PA6
9 |<-| CPU PA5
10 |<-| CPU PA4
11 |<-| CPU PA3
12 |<-| CPU PA2
13 |<-| CPU PA1
14 |<-| CPU PA0
15 |<>| CPU D0 (PCE) or D7 (TG16)
16 |<>| CPU D1 (PCE) or D6 (TG16)
17 |<>| CPU D2 (PCE) or D5 (TG16)
18 |--| GND
19 |<>| CPU D3 (PCE) or D4 (TG16)
20 |<>| CPU D4 (PCE) or D3 (TG16)
21 |<>| CPU D5 (PCE) or D2 (TG16)
22 |<>| CPU D6 (PCE) or D1 (TG16)
23 |<>| CPU D7 (PCE) or D0 (TG16) Orientation:
24 |<-| CPU PA20 --------------------------
25 |<-| CPU PA10 .-------------------.
26 |<-| CPU /RD | .---------..------|
27 |<-| CPU PA11 | | || |- 1
28 |<-| CPU PA9 |>| Label || |
29 |<-| CPU PA8 | | || |- 38
30 |<-| CPU PA13 | '---------<nowiki>''</nowiki>------|
31 |<-| CPU PA14 '-------------------'
32 |<-| CPU PA17
33 |<-| CPU PA18 Legend:
34 |<-| CPU /WR --------------------------
35 |<-| HSM [HuCard]-- Power, n/a
36 |<-| /RST [HuCard]<- HuCard input
37 |->| /IRQ2 [HuCard]-> HuCard output
38 |--| +5V [HuCard]<> Bidirectional
==Signal descriptions==
* '''/CD''': Card detect. Connects to the expansion port. Grounded by the HuCard so the CD-ROM<sup>2</sup> can tell a card is inserted.
* '''AUDIO IN''': Mono audio. Mixed into both channels.
* '''CPU PA20..0''': CPU physical address (the 21-bit post-MMU address). PA20 is used as /CE.
* '''CPU D7..0''': The order of these pins depends on region. For PC-Engine, they are ascending, and for TurboGrafx-16, they are descending.
* '''HSM''': High speed mode, asserted by the CPU when operating at 7.16 MHz.
3950b596af549595efabd7cab36f892981ba7b33
24
11
2023-08-28T13:26:35Z
Fiskbit
37
No dash in PC Engine.
wikitext
text/x-wiki
==Pinout==
Card | | PC Engine
-----+--+--------------------------
1 |->| /CD
2 |->| AUDIO IN
3 |<-| CPU PA19
4 |<-| CPU PA16
5 |<-| CPU PA15
6 |<-| CPU PA12
7 |<-| CPU PA7
8 |<-| CPU PA6
9 |<-| CPU PA5
10 |<-| CPU PA4
11 |<-| CPU PA3
12 |<-| CPU PA2
13 |<-| CPU PA1
14 |<-| CPU PA0
15 |<>| CPU D0 (PCE) or D7 (TG16)
16 |<>| CPU D1 (PCE) or D6 (TG16)
17 |<>| CPU D2 (PCE) or D5 (TG16)
18 |--| GND
19 |<>| CPU D3 (PCE) or D4 (TG16)
20 |<>| CPU D4 (PCE) or D3 (TG16)
21 |<>| CPU D5 (PCE) or D2 (TG16)
22 |<>| CPU D6 (PCE) or D1 (TG16)
23 |<>| CPU D7 (PCE) or D0 (TG16) Orientation:
24 |<-| CPU PA20 --------------------------
25 |<-| CPU PA10 .-------------------.
26 |<-| CPU /RD | .---------..------|
27 |<-| CPU PA11 | | || |- 1
28 |<-| CPU PA9 |>| Label || |
29 |<-| CPU PA8 | | || |- 38
30 |<-| CPU PA13 | '---------<nowiki>''</nowiki>------|
31 |<-| CPU PA14 '-------------------'
32 |<-| CPU PA17
33 |<-| CPU PA18 Legend:
34 |<-| CPU /WR --------------------------
35 |<-| HSM [HuCard]-- Power, n/a
36 |<-| /RST [HuCard]<- HuCard input
37 |->| /IRQ2 [HuCard]-> HuCard output
38 |--| +5V [HuCard]<> Bidirectional
==Signal descriptions==
* '''/CD''': Card detect. Connects to the expansion port. Grounded by the HuCard so the CD-ROM<sup>2</sup> can tell a card is inserted.
* '''AUDIO IN''': Mono audio. Mixed into both channels.
* '''CPU PA20..0''': CPU physical address (the 21-bit post-MMU address). PA20 is used as /CE.
* '''CPU D7..0''': The order of these pins depends on region. For PC Engine, they are ascending, and for TurboGrafx-16, they are descending.
* '''HSM''': High speed mode, asserted by the CPU when operating at 7.16 MHz.
375b7b3e32f22e15a803ac3125eeb44d88dd5f4a
VDC pinout
0
7
9
2023-08-16T07:50:40Z
Fiskbit
37
Adds VDC pinout.
wikitext
text/x-wiki
==Pinout==
^
/ \
/ \
/ \
/CS -> / 1 80 \ <- CPU PA1
CPU /WR -> / 2 79 \ <- CPU PA0
CPU /RD -> / 3 78 \ -> /BUSY
CPU D15 <> / 4 O 77 \ -> /IRQ
CPU D14 <> / 5 76 \ -> MA15
CPU D13 <> / 6 75 \ -> MA14
CPU D12 <> / 7 74 \ -> MA13
CPU D11 <> / 8 73 \ -> MA12
CPU D10 <> / 9 72 \ -- +5V (VDD4)
CPU D9 <> / 10 71 \ -- GND (VSS4)
GND (VSS1) -- / 11 70 \ -> MA11
CPU D8 <> / 12 69 \ -> MA10
CPU D7 <> / 13 68 \ -> MA9
CPU D6 <> / 14 67 \ -> MA8
CPU D5 <> / 15 66 \ -> MA7
CPU D4 <> / 16 65 \ -> MA6
CPU D3 <> / 17 \
+5V (VDD1) -- / 18 /
CPU D2 <> / 19 64 / -> MA5
CPU D1 <> / 20 63 / -> MA4
CPU D0 <> / 21 HuC6270 HUDSON 62 / -> MA3
8/16 -> / 22 Package QFP-80 61 / -> MA2
CK -> / 23 60 / -> MA1
/RST -> / 24 59 / -> MA0
/ 58 / <> MD15
\ 57 / <> MD14
/VSYN -> \ 25 56 / <> MD13
/HSYN -> \ 26 55 / -- GND (VSS3) Orientation:
DISP <- \ 27 54 / <> MD12 --------------------
SPBG <- \ 28 53 / <> MD11 64 41
VD7 <- \ 29 52 / <> MD10 | |
VD6 <- \ 30 51 / <> MD9 .-----------.
VD5 <- \ 31 50 / <> MD8 65-| O|-40
+5V (VDD2) -- \ 32 49 / <> MD7 | HuC6270|
GND (VSS2) -- \ 33 48 / <> MD6 80-|O HUDSON |-25
VD4 <- \ 34 47 / -- +5V (VDD3) '-----------'
VD3 <- \ 35 46 / <> MD5 | |
VD2 <- \ 36 45 / <> MD4 01 24
VD1 <- \ 37 O 44 / <> MD3
VD0 <- \ 38 43 / <> MD2 Legend:
/MWR <- \ 39 42 / <> MD1 ----------------------------
/MRD <- \ 40 41 / <> MD0 --[HuC6270]-- Power, n/a
\ / ->[HuC6270]<- HuC6270 input
\ / <-[HuC6270]-> HuC6270 output
\ / <>[HuC6270]<> Bidirectional
V
==Signal descriptions==
* '''CK''': Input clock from the VEC, configured by the CPU.
* '''/CS''': Chip select. Connected to CPU /CE7, selecting the VDC when writing to $FF:$0000-$03FF.
* '''8/16''': Controls CPU data bus width. This is connected to +5V.
* '''CPU D15..8''': The upper half of the CPU data bus when operating in 16-bit mode. However, the PC-Engine uses 8-bit mode exclusively, so these are not connected.
* '''/IRQ''': Interrupt output to the CPU.
* '''/BUSY''': Asserted during CPU writes until the VDC is able to service the write. Connected to CPU RDY.
* '''MA15..0''': The VDC VRAM address bus.
* '''MD15..0''': The VDC VRAM data bus.
* '''/MRD''', '''/MWR''': Indicates read and write on the VDC VRAM bus.
* '''SPBG''', '''VD7..0''': The 9-bit color index output to the VCE. SPBG acts as bit 8. High for sprites and low for backgrounds.
* '''/HSYN''', '''/VSYN''': Horizontal and vertical sync from the VCE, to which the VDC synchronizes its video output.
* '''DISP''': A test output indicating different regions of the picture, configured through control register (CR, register $05) and normally not connected:
** CR.9..8 = 00: DISP - asserted during active pixels.
** CR.9..8 = 01: BURST - deasserted during color burst.
** CR.9..8 = 10: INTHSYNC - outputs the internal horizontal sync signal.
** CR.9..8 = 11: (unused)
db398460f074d533468be9e5e7a1d14e39c1b2ef
23
9
2023-08-28T13:26:06Z
Fiskbit
37
No dash in PC Engine.
wikitext
text/x-wiki
==Pinout==
^
/ \
/ \
/ \
/CS -> / 1 80 \ <- CPU PA1
CPU /WR -> / 2 79 \ <- CPU PA0
CPU /RD -> / 3 78 \ -> /BUSY
CPU D15 <> / 4 O 77 \ -> /IRQ
CPU D14 <> / 5 76 \ -> MA15
CPU D13 <> / 6 75 \ -> MA14
CPU D12 <> / 7 74 \ -> MA13
CPU D11 <> / 8 73 \ -> MA12
CPU D10 <> / 9 72 \ -- +5V (VDD4)
CPU D9 <> / 10 71 \ -- GND (VSS4)
GND (VSS1) -- / 11 70 \ -> MA11
CPU D8 <> / 12 69 \ -> MA10
CPU D7 <> / 13 68 \ -> MA9
CPU D6 <> / 14 67 \ -> MA8
CPU D5 <> / 15 66 \ -> MA7
CPU D4 <> / 16 65 \ -> MA6
CPU D3 <> / 17 \
+5V (VDD1) -- / 18 /
CPU D2 <> / 19 64 / -> MA5
CPU D1 <> / 20 63 / -> MA4
CPU D0 <> / 21 HuC6270 HUDSON 62 / -> MA3
8/16 -> / 22 Package QFP-80 61 / -> MA2
CK -> / 23 60 / -> MA1
/RST -> / 24 59 / -> MA0
/ 58 / <> MD15
\ 57 / <> MD14
/VSYN -> \ 25 56 / <> MD13
/HSYN -> \ 26 55 / -- GND (VSS3) Orientation:
DISP <- \ 27 54 / <> MD12 --------------------
SPBG <- \ 28 53 / <> MD11 64 41
VD7 <- \ 29 52 / <> MD10 | |
VD6 <- \ 30 51 / <> MD9 .-----------.
VD5 <- \ 31 50 / <> MD8 65-| O|-40
+5V (VDD2) -- \ 32 49 / <> MD7 | HuC6270|
GND (VSS2) -- \ 33 48 / <> MD6 80-|O HUDSON |-25
VD4 <- \ 34 47 / -- +5V (VDD3) '-----------'
VD3 <- \ 35 46 / <> MD5 | |
VD2 <- \ 36 45 / <> MD4 01 24
VD1 <- \ 37 O 44 / <> MD3
VD0 <- \ 38 43 / <> MD2 Legend:
/MWR <- \ 39 42 / <> MD1 ----------------------------
/MRD <- \ 40 41 / <> MD0 --[HuC6270]-- Power, n/a
\ / ->[HuC6270]<- HuC6270 input
\ / <-[HuC6270]-> HuC6270 output
\ / <>[HuC6270]<> Bidirectional
V
==Signal descriptions==
* '''CK''': Input clock from the VEC, configured by the CPU.
* '''/CS''': Chip select. Connected to CPU /CE7, selecting the VDC when writing to $FF:$0000-$03FF.
* '''8/16''': Controls CPU data bus width. This is connected to +5V.
* '''CPU D15..8''': The upper half of the CPU data bus when operating in 16-bit mode. However, the PC Engine uses 8-bit mode exclusively, so these are not connected.
* '''/IRQ''': Interrupt output to the CPU.
* '''/BUSY''': Asserted during CPU writes until the VDC is able to service the write. Connected to CPU RDY.
* '''MA15..0''': The VDC VRAM address bus.
* '''MD15..0''': The VDC VRAM data bus.
* '''/MRD''', '''/MWR''': Indicates read and write on the VDC VRAM bus.
* '''SPBG''', '''VD7..0''': The 9-bit color index output to the VCE. SPBG acts as bit 8. High for sprites and low for backgrounds.
* '''/HSYN''', '''/VSYN''': Horizontal and vertical sync from the VCE, to which the VDC synchronizes its video output.
* '''DISP''': A test output indicating different regions of the picture, configured through control register (CR, register $05) and normally not connected:
** CR.9..8 = 00: DISP - asserted during active pixels.
** CR.9..8 = 01: BURST - deasserted during color burst.
** CR.9..8 = 10: INTHSYNC - outputs the internal horizontal sync signal.
** CR.9..8 = 11: (unused)
baa872a60f3c9c66735f80058f4afbd69352d746
Main Page
0
8
16
2023-08-23T09:18:22Z
Fiskbit
37
Fiskbit moved page [[Main Page]] to [[PCEdev Wiki]]: Rename main page to match wiki name.
wikitext
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#REDIRECT [[PCEdev Wiki]]
a56be20375d899701049bf70d430a893218930a4
MediaWiki:Mainpage
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9
17
2023-08-23T09:18:40Z
Fiskbit
37
Point to the new main page name.
wikitext
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PCEdev Wiki
33be233c632448913f4520068c61efa95423e177
CPU memory map
0
10
21
2023-08-28T13:25:20Z
Fiskbit
37
Adds initial CPU memory map.
wikitext
text/x-wiki
== Virtual address space ==
{| class="tabular"
! Address || Purpose
|-
| $2000-$20FF || Zero page
|-
| $2100-$21FF || Stack
|-
| $FFF6-$FFF7 || IRQ2/BRK vector
|-
| $FFF8-$FFF9 || IRQ1 vector
|-
| $FFFA-$FFFB || Timer vector
|-
| $FFFC-$FFFD || NMI vector
|-
| $FFFE-$FFFF || Reset vector
|}
The zero page, stack, and vectors exist at fixed locations within the virtual address space. The physical memory backing these can be swapped to any bank at any time, but the virtual addresses cannot be changed. The rest of the virtual address space has no special meaning to the hardware.
== Physical address space ==
The physical address space varies by console type. The following mapping applies to the PC Engine, CoreGrafx, CoreGrafx II, and TurboGrafx-16. Differences and additions to this in other variants are documented in sections below.
{| class="tabular"
! Bank || Device
|-
| $00-$7F || HuCard
|-
| $80-$F7 || (unmapped)
|-
| $F8 || RAM (8 KiB)
|-
| $F9-$FB || RAM mirrors
|-
| $FC-FE || (unmapped)
|-
| $FF || Hardware registers
|}
{| class="tabular"
! Bank $FF offset || Device
|-
| $0000-$03FF || VDC (4 registers mirrored)
|-
| $0400-$07FF || VCE (8 registers mirrored)
|-
| $0800-$0BFF || PSG
|-
| $0C00-$0FFF || Timer (2 registers mirrored)
|-
| $1000-$13FF || I/O port (1 register mirrored)
|-
| $1400-$17FF || Interrupt controller (4 registers mirrored)
|-
| $1800-$1FFF || (unmapped)
|}
Any unmapped address in physical memory can potentially be mapped by an expansion port device or a HuCard, but most HuCards lack any sort of memory mapper and simply use the highest address bit as a chip enable.
=== SuperGrafx ===
{| class="tabular"
! Bank || Device
|-
| $F8-$FB || RAM (32 KiB)
|}
{| class="tabular"
! Bank $FF offset || Device
|-
| $0000-$0007 || VDC1 registers
|-
| $0008-$000F || VPC registers
|-
| $0010-$0017 || VDC2 registers
|-
| $0018-$001F || (unmapped)
|-
| $0020-$03FF || Mirrors of $0000-$001F
|}
fece469341fb90fc4391046c22387f8fad8344ec
32
21
2023-08-28T14:59:48Z
Asie
351
Combine physical address space tables, separate hardware register bank tables.
wikitext
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== Virtual address space ==
{| class="tabular"
! Address || Purpose
|-
| $2000-$20FF || Zero page
|-
| $2100-$21FF || Stack
|-
| $FFF6-$FFF7 || IRQ2/BRK vector
|-
| $FFF8-$FFF9 || IRQ1 vector
|-
| $FFFA-$FFFB || Timer vector
|-
| $FFFC-$FFFD || NMI vector
|-
| $FFFE-$FFFF || Reset vector
|}
The zero page, stack, and vectors exist at fixed locations within the virtual address space. The physical memory backing these can be swapped to any bank at any time, but the virtual addresses cannot be changed. The rest of the virtual address space has no special meaning to the hardware.
== Physical address space ==
The physical address space varies by console type.
{| class="tabular"
! Bank || PC Engine || SuperGrafx || PC Engine CD
|-
| $00-$7F
| colspan="3" style="text-align:center;" | HuCard
|-
| $80-$87
| colspan="2" style="text-align:center;" | (unmapped)
| style="text-align:center;" | RAM (64 KiB)
|-
| $88-$F7
| colspan="3" style="text-align:center;" | (unmapped)
|-
| $F8
| colspan="3" style="text-align:center;" | RAM (8 KiB)
|-
| $F9-$FB
| style="text-align:center;" | RAM mirrors
| style="text-align:center;" | RAM (24 KiB)
|
|-
| $FC-FE
| colspan="3" style="text-align:center;" | (unmapped)
|-
| $FF
| colspan="3" style="text-align:center;" | Hardware registers
|}
Note that a PC Engine CD can be connected to the SuperGrafx as well - created a layout in which both the PC Engine CD's 64 KiB of additional RAM and the SuperGrafx's 24 KiB of additional RAM are available.
== Hardware register bank ==
=== PC Engine ===
{| class="tabular"
! Bank $FF offset || Device
|-
| $0000-$03FF || VDC (4 registers mirrored)
|-
| $0400-$07FF || VCE (8 registers mirrored)
|-
| $0800-$0BFF || PSG
|-
| $0C00-$0FFF || Timer (2 registers mirrored)
|-
| $1000-$13FF || I/O port (1 register mirrored)
|-
| $1400-$17FF || Interrupt controller (4 registers mirrored)
|-
| $1800-$1FFF || (unmapped)
|}
Any unmapped address in physical memory can potentially be mapped by an expansion port device or a HuCard, but most HuCards lack any sort of memory mapper and simply use the highest address bit as a chip enable.
=== SuperGrafx ===
{| class="tabular"
! Bank $FF offset || Device
|-
| $0000-$0007 || VDC1 registers
|-
| $0008-$000F || VPC registers
|-
| $0010-$0017 || VDC2 registers
|-
| $0018-$001F || (unmapped)
|-
| $0020-$03FF || Mirrors of $0000-$001F
|}
=== PC Engine CD ===
{| class="tabular"
! Bank $FF offset || Device
|-
| $1800-$180F || CD interface registers
|}
TODO: Do any mirrors exist?
871ffa941b627209989cda33f247dfd0df4e45d3
CPU addresses
0
11
25
2023-08-28T13:34:31Z
Fiskbit
37
Adds explanation of CPU addresses and terms.
wikitext
text/x-wiki
The PC Engine CPU uses 2 kinds of addresses: The 65C02 core operates on 16-bit addresses, and these get translated by a memory management unit (MMU) into 21-bit addresses. The console's devices are mapped into this [[CPU memory map#Physical address space|21-bit address space]]. We refer to the 65C02 core's 16-bit addresses as '''virtual addresses''', and the 21-bit addresses used everywhere else as '''physical addresses'''.
The virtual address space is split into 8 8-KiB regions called '''pages'''. Each page is mapped by the MMU to one of 256 8-KiB regions called '''banks'''. Any page can be mapped to any bank. The 13-bit address within a page or bank is called an '''offset''', and the 21-bit physical address can be represented as a combination of the 8-bit bank and 13-bit offset, such as $81:1FFF to refer to $103FFF.
Note that "page" is also used to refer to 256-byte regions within the 65C02's address space, but this is only relevant in the context of '''zero page''' and the '''stack page'''; "page" can be assumed to be an 8 KiB region otherwise.
f2a63498dfaf1a69eba23ddc9badc54522079518
Category:Deletion requests
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12
28
2023-08-28T13:39:24Z
Fiskbit
37
Adds deletion-request category.
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text/x-wiki
This is a list of pages including the <nowiki>{{delete}}</nowiki> template, requesting a moderator to review them for deletion.
See: [[Template:Delete]]
f5fc73d29d81cdb615aefd3b4fd885759b595dfb
Template:Delete
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13
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2023-08-28T13:40:01Z
Fiskbit
37
Adds deletion-request template.
wikitext
text/x-wiki
<noinclude>Place this template on a page that you think should be deleted.
For a list of pending deletion requests see: [[:Category:Deletion requests]]
</noinclude>'''''This page is requested for deletion review by a moderator.'''''
<includeonly>[[Category:Deletion requests]]</includeonly>
97de1a9d59533764786c50377a5383f61fabc645
Template:Anchor
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14
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2023-08-28T13:41:16Z
Fiskbit
37
Adds anchor template.
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{{#if:{{{1|<noinclude>1</noinclude>}}}|<ins id="{{{1|<noinclude>test-anchor</noinclude>}}}"></ins>}}<!--
-->{{#if:{{{2|}}}|<ins id="{{{2|}}}"></ins>}}<!--
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-->{{#if:{{{11|}}}|<span class="error">[[Template:Anchor]]: Too many anchors; maximum is 10.</span>}}<noinclude>{{Template:Anchor/doc}}</noinclude>
d19deedb0ebb921c0b7614951d0382695f54fea1
Template:Anchor/doc
10
15
31
2023-08-28T13:41:45Z
Fiskbit
37
Adds anchor template doc.
wikitext
text/x-wiki
{| class="wikitable"
| This documentation is at: [[Template:Anchor/doc]]
|}
This template manually adds one or more HTML anchors, allowing links to locations other than section headings.
Usage can create a single named anchor, or many at the same location:
<code><nowiki>
{{Anchor|name1}}
</nowiki></code>
<code><nowiki>
{{Anchor|name1|name2|name3...}}
</nowiki></code>
Linking can be used within the same page, or in cross-page links:
<code><nowiki>
[[#name1|name1]]
</nowiki></code>
<code><nowiki>
[[Pagename#name1|name1]]
</nowiki></code>
8b491fdabd76e3517387ebf5622d363ea3ac766b
Timing
0
16
34
2023-08-28T15:43:38Z
Asie
351
Created page with "The (NTSC) PC Engine is clocked with a master clock equal to six times the NTSC color burst (<code>315/88</code> MHz), or approximately 21.47727 MHz. This is divided into the following clocks: * CPU "high" clock speed = master clock / 3 (approx. 7.15909 MHz), * CPU "low" clock speed = master clock / 12 (approx. 1.78978 MHz), * Timer speed = master clock / 3072 (approx. 6.991 KHz), * VCE pixel clocks: ** "10MHz" = master clock / 2, ** "7MHz" = master clock / 3, ** "5MHz..."
wikitext
text/x-wiki
The (NTSC) PC Engine is clocked with a master clock equal to six times the NTSC color burst (<code>315/88</code> MHz), or approximately 21.47727 MHz.
This is divided into the following clocks:
* CPU "high" clock speed = master clock / 3 (approx. 7.15909 MHz),
* CPU "low" clock speed = master clock / 12 (approx. 1.78978 MHz),
* Timer speed = master clock / 3072 (approx. 6.991 KHz),
* VCE pixel clocks:
** "10MHz" = master clock / 2,
** "7MHz" = master clock / 3,
** "5MHz" = master clock / 4.
d5e7afa815245fa8254d4e6133ed44480ba849e6
VCE pinout
0
17
36
2023-08-29T09:05:36Z
Fiskbit
37
Adds VCE pinout. Still need to figure out how to document the analog power connections.
wikitext
text/x-wiki
== Pinout ==
^
/ \
/ \
/ \
+5V (D) -- / 1 80 \ <- 8/16
OSC -> / 2 79 \ <- /CS
GND (D) -- / 3 78 \ <- CPU /RD
CPU D8 <> / 4 O 77 \ <- CPU /WR
CPU D7 <> / 5 76 \ <- CPU PA2
CPU D6 <> / 6 75 \ <- CPU PA1
CPU D5 <> / 7 74 \ <- CPU PA0
CPU D4 <> / 8 73 \ -> CK
CPU D3 <> / 9 72 \ -> /VSYN
CPU D2 <> / 10 71 \ -> /HSYN
CPU D1 <> / 11 70 \ <- VD8
CPU D0 <> / 12 69 \ <- VD7
+5V (D) -- / 13 68 \ <- VD6
GND (D) -- / 14 67 \ <- VD5
GND (D) -- / 15 66 \ <- VD4
+5V (D) -- / 16 65 \ <- VD3
BRT- -> / 17 \
BRTC <> / 18 /
GND (A) -- / 19 64 / <- VD2
BURS <- / 20 63 / <- VD1
+5V (A) -- / 21 HuC6260 HUDSON 62 / <- VD0
BRT+ -> / 22 Package QFP-80 61 / <- SEL
B-Y- <> / 23 60 / ?? TEST3
B-YC <> / 24 59 / <- TEST2 (YUV HI/LO)
/ 58 / <- TEST1 (PAL/YUV)
\ 57 / -- +5V (D)
GND (A) -- \ 25 56 / -- GND (D) Orientation:
B-Y <- \ 26 55 / -- GND (D) --------------------
+5V (A) -- \ 27 54 / -- +5V (D) 64 41
B-Y+ -> \ 28 53 / -- +5V (D) | |
GND (A) -- \ 29 52 / <- RGB+ .-----------.
R-Y- <> \ 30 51 / -> B 65-| O|-40
R-YC <> \ 31 50 / -- +5V (A) | HuC6260|
GND (A) -- \ 32 49 / -> R 80-|O HUDSON |-25
R-Y <- \ 33 48 / -- GND (A) '-----------'
+5V (A) -- \ 34 47 / -> G | |
R-Y+ -> \ 35 46 / <> RGB- 01 24
+5V (A) -- \ 36 45 / <- SYN+
Y- <> \ 37 O 44 / -> SYNC Legend:
YC <> \ 38 43 / <> SYN- ----------------------------
GND (A) -- \ 39 42 / <- Y+ --[HuC6260]-- Power, n/a
Y <- \ 40 41 / -- +5V (A) ->[HuC6260]<- HuC6260 input
\ / <-[HuC6260]-> HuC6260 output
\ / <>[HuC6260]<> Bidirectional
\ / ??[HuC6260]?? Unknown
V
== Signal descriptions ==
* '''+5V (A)''', '''GND (A)''': Power for analog signals.
* '''+5V (D)''', '''GND (D)''': Power for digital signals.
* '''OSC''': 21.4772 MHz clock input.
* '''CK''': Output clock for the VDC, configured by the CPU.
* '''/CS''': Chip select. Connected to CPU CEK, selecting the VDC when writing to $FF:$0400-$07FF.
* '''8/16''': Controls CPU data bus width. This is connected to +5V (8-bit mode).
* '''CPU D8''': Used in 16-bit mode. However, the PC-Engine uses 8-bit mode exclusively, so this is not connected.
* '''VD8..VD0''': 9-bit color input from the VDC. VD8 is connected to the VDC's SPBG output.
* '''/HSYN''', '''/VSYN''': Horizontal and vertical sync for the VDC, to which the VDC synchronizes its video output.
* '''SEL''': 'Output Control' or 'Video Select'. Deasserting may disable VCE video output. Connected to the expansion port, but normally floating externally.
* '''TEST1''' ('''PAL/YUV'''): When grounded, reading palette RAM returns data from the YUV ROM, instead. The YUV ROM is indexed using the value at the palette RAM address being read by the CPU. This pin is normally not connected.<ref>[http://furrtek.free.fr/?a=pceyuv furrtek]: Dumping the NEC PC Engine YUV table</ref>
* '''TEST2''' ('''YUV HI/LO'''): Controls which half of the 15-bit YUV value is returned to the CPU when reading from YUV ROM. When reading the high byte, bit 7 is always 0. This pin is normally not connected.
* '''TEST3''': This appears to have a function, but its behavior is unknown. Normally not connected.
Note: Pins appear to be pulled up internally, so not connected pins are high.
== References ==
<references />
fc9191c385ce0dbbd2b0ff2dd18e3e5431132b8c
38
36
2023-08-29T13:52:03Z
Fiskbit
37
Removes unnecessary indentation. Uses named reference to add reference link for TEST2.
wikitext
text/x-wiki
== Pinout ==
^
/ \
/ \
/ \
+5V (D) -- / 1 80 \ <- 8/16
OSC -> / 2 79 \ <- /CS
GND (D) -- / 3 78 \ <- CPU /RD
CPU D8 <> / 4 O 77 \ <- CPU /WR
CPU D7 <> / 5 76 \ <- CPU PA2
CPU D6 <> / 6 75 \ <- CPU PA1
CPU D5 <> / 7 74 \ <- CPU PA0
CPU D4 <> / 8 73 \ -> CK
CPU D3 <> / 9 72 \ -> /VSYN
CPU D2 <> / 10 71 \ -> /HSYN
CPU D1 <> / 11 70 \ <- VD8
CPU D0 <> / 12 69 \ <- VD7
+5V (D) -- / 13 68 \ <- VD6
GND (D) -- / 14 67 \ <- VD5
GND (D) -- / 15 66 \ <- VD4
+5V (D) -- / 16 65 \ <- VD3
BRT- -> / 17 \
BRTC <> / 18 /
GND (A) -- / 19 64 / <- VD2
BURS <- / 20 63 / <- VD1
+5V (A) -- / 21 HuC6260 HUDSON 62 / <- VD0
BRT+ -> / 22 Package QFP-80 61 / <- SEL
B-Y- <> / 23 60 / ?? TEST3
B-YC <> / 24 59 / <- TEST2 (YUV HI/LO)
/ 58 / <- TEST1 (PAL/YUV)
\ 57 / -- +5V (D)
GND (A) -- \ 25 56 / -- GND (D) Orientation:
B-Y <- \ 26 55 / -- GND (D) --------------------
+5V (A) -- \ 27 54 / -- +5V (D) 64 41
B-Y+ -> \ 28 53 / -- +5V (D) | |
GND (A) -- \ 29 52 / <- RGB+ .-----------.
R-Y- <> \ 30 51 / -> B 65-| O|-40
R-YC <> \ 31 50 / -- +5V (A) | HuC6260|
GND (A) -- \ 32 49 / -> R 80-|O HUDSON |-25
R-Y <- \ 33 48 / -- GND (A) '-----------'
+5V (A) -- \ 34 47 / -> G | |
R-Y+ -> \ 35 46 / <> RGB- 01 24
+5V (A) -- \ 36 45 / <- SYN+
Y- <> \ 37 O 44 / -> SYNC Legend:
YC <> \ 38 43 / <> SYN- ----------------------------
GND (A) -- \ 39 42 / <- Y+ --[HuC6260]-- Power, n/a
Y <- \ 40 41 / -- +5V (A) ->[HuC6260]<- HuC6260 input
\ / <-[HuC6260]-> HuC6260 output
\ / <>[HuC6260]<> Bidirectional
\ / ??[HuC6260]?? Unknown
V
== Signal descriptions ==
* '''+5V (A)''', '''GND (A)''': Power for analog signals.
* '''+5V (D)''', '''GND (D)''': Power for digital signals.
* '''OSC''': 21.4772 MHz clock input.
* '''CK''': Output clock for the VDC, configured by the CPU.
* '''/CS''': Chip select. Connected to CPU CEK, selecting the VDC when writing to $FF:$0400-$07FF.
* '''8/16''': Controls CPU data bus width. This is connected to +5V (8-bit mode).
* '''CPU D8''': Used in 16-bit mode. However, the PC-Engine uses 8-bit mode exclusively, so this is not connected.
* '''VD8..VD0''': 9-bit color input from the VDC. VD8 is connected to the VDC's SPBG output.
* '''/HSYN''', '''/VSYN''': Horizontal and vertical sync for the VDC, to which the VDC synchronizes its video output.
* '''SEL''': 'Output Control' or 'Video Select'. Deasserting may disable VCE video output. Connected to the expansion port, but normally floating externally.
* '''TEST1''' ('''PAL/YUV'''): When grounded, reading palette RAM returns data from the YUV ROM, instead. The YUV ROM is indexed using the value at the palette RAM address being read by the CPU. This pin is normally not connected.<ref name="yuv">[http://furrtek.free.fr/?a=pceyuv furrtek]: Dumping the NEC PC Engine YUV table</ref>
* '''TEST2''' ('''YUV HI/LO'''): Controls which half of the 15-bit YUV value is returned to the CPU when reading from YUV ROM. When reading the high byte, bit 7 is always 0. This pin is normally not connected.<ref name="yuv" />
* '''TEST3''': This appears to have a function, but its behavior is unknown. Normally not connected.
Note: Pins appear to be pulled up internally, so not connected pins are high.
== References ==
<references />
4f8b1f1cf4e455a86b06ba36ce45f7b34d3116cc
39
38
2023-08-31T10:39:57Z
Fiskbit
37
Adds lidnariq's SEL findings.
wikitext
text/x-wiki
== Pinout ==
^
/ \
/ \
/ \
+5V (D) -- / 1 80 \ <- 8/16
OSC -> / 2 79 \ <- /CS
GND (D) -- / 3 78 \ <- CPU /RD
CPU D8 <> / 4 O 77 \ <- CPU /WR
CPU D7 <> / 5 76 \ <- CPU PA2
CPU D6 <> / 6 75 \ <- CPU PA1
CPU D5 <> / 7 74 \ <- CPU PA0
CPU D4 <> / 8 73 \ -> CK
CPU D3 <> / 9 72 \ -> /VSYN
CPU D2 <> / 10 71 \ -> /HSYN
CPU D1 <> / 11 70 \ <- VD8
CPU D0 <> / 12 69 \ <- VD7
+5V (D) -- / 13 68 \ <- VD6
GND (D) -- / 14 67 \ <- VD5
GND (D) -- / 15 66 \ <- VD4
+5V (D) -- / 16 65 \ <- VD3
BRT- -> / 17 \
BRTC <> / 18 /
GND (A) -- / 19 64 / <- VD2
BURS <- / 20 63 / <- VD1
+5V (A) -- / 21 HuC6260 HUDSON 62 / <- VD0
BRT+ -> / 22 Package QFP-80 61 / <- SEL
B-Y- <> / 23 60 / ?? TEST3
B-YC <> / 24 59 / <- TEST2 (YUV HI/LO)
/ 58 / <- TEST1 (PAL/YUV)
\ 57 / -- +5V (D)
GND (A) -- \ 25 56 / -- GND (D) Orientation:
B-Y <- \ 26 55 / -- GND (D) --------------------
+5V (A) -- \ 27 54 / -- +5V (D) 64 41
B-Y+ -> \ 28 53 / -- +5V (D) | |
GND (A) -- \ 29 52 / <- RGB+ .-----------.
R-Y- <> \ 30 51 / -> B 65-| O|-40
R-YC <> \ 31 50 / -- +5V (A) | HuC6260|
GND (A) -- \ 32 49 / -> R 80-|O HUDSON |-25
R-Y <- \ 33 48 / -- GND (A) '-----------'
+5V (A) -- \ 34 47 / -> G | |
R-Y+ -> \ 35 46 / <> RGB- 01 24
+5V (A) -- \ 36 45 / <- SYN+
Y- <> \ 37 O 44 / -> SYNC Legend:
YC <> \ 38 43 / <> SYN- ----------------------------
GND (A) -- \ 39 42 / <- Y+ --[HuC6260]-- Power, n/a
Y <- \ 40 41 / -- +5V (A) ->[HuC6260]<- HuC6260 input
\ / <-[HuC6260]-> HuC6260 output
\ / <>[HuC6260]<> Bidirectional
\ / ??[HuC6260]?? Unknown
V
== Signal descriptions ==
* '''+5V (A)''', '''GND (A)''': Power for analog signals.
* '''+5V (D)''', '''GND (D)''': Power for digital signals.
* '''OSC''': 21.4772 MHz clock input.
* '''CK''': Output clock for the VDC, configured by the CPU.
* '''/CS''': Chip select. Connected to CPU CEK, selecting the VDC when writing to $FF:$0400-$07FF.
* '''8/16''': Controls CPU data bus width. This is connected to +5V (8-bit mode).
* '''CPU D8''': Used in 16-bit mode. However, the PC-Engine uses 8-bit mode exclusively, so this is not connected.
* '''VD8..VD0''': 9-bit color input from the VDC. VD8 is connected to the VDC's SPBG output.
* '''/HSYN''', '''/VSYN''': Horizontal and vertical sync for the VDC, to which the VDC synchronizes its video output.
* '''SEL''': 'Output Control' or 'Video Select'. Deasserting makes /HSYN, /VSYN, and CK go high impedance, freezing output from the VDC, but the VCE still draws VD8..0 input as normal. Connected to the expansion port (along with /HSYN, /VSYN, and CK), but normally floating externally.
* '''TEST1''' ('''PAL/YUV'''): When grounded, reading palette RAM returns data from the YUV ROM, instead. The YUV ROM is indexed using the value at the palette RAM address being read by the CPU. This pin is normally not connected.<ref name="yuv">[http://furrtek.free.fr/?a=pceyuv furrtek]: Dumping the NEC PC Engine YUV table</ref>
* '''TEST2''' ('''YUV HI/LO'''): Controls which half of the 15-bit YUV value is returned to the CPU when reading from YUV ROM. When reading the high byte, bit 7 is always 0. This pin is normally not connected.<ref name="yuv" />
* '''TEST3''': This appears to have a function, but its behavior is unknown. Normally not connected.
Note: Pins appear to be pulled up internally, so not connected pins are high.
== References ==
<references />
e9ea5b8bad7c11cbfcdf83970644fc7e33ab7609
40
39
2023-09-01T12:48:22Z
Fiskbit
37
Changes SEL to VCESEL for clarity. More clarification on how it can be used.
wikitext
text/x-wiki
== Pinout ==
^
/ \
/ \
/ \
+5V (D) -- / 1 80 \ <- 8/16
OSC -> / 2 79 \ <- /CS
GND (D) -- / 3 78 \ <- CPU /RD
CPU D8 <> / 4 O 77 \ <- CPU /WR
CPU D7 <> / 5 76 \ <- CPU PA2
CPU D6 <> / 6 75 \ <- CPU PA1
CPU D5 <> / 7 74 \ <- CPU PA0
CPU D4 <> / 8 73 \ -> CK
CPU D3 <> / 9 72 \ -> /VSYN
CPU D2 <> / 10 71 \ -> /HSYN
CPU D1 <> / 11 70 \ <- VD8
CPU D0 <> / 12 69 \ <- VD7
+5V (D) -- / 13 68 \ <- VD6
GND (D) -- / 14 67 \ <- VD5
GND (D) -- / 15 66 \ <- VD4
+5V (D) -- / 16 65 \ <- VD3
BRT- -> / 17 \
BRTC <> / 18 /
GND (A) -- / 19 64 / <- VD2
BURS <- / 20 63 / <- VD1
+5V (A) -- / 21 HuC6260 HUDSON 62 / <- VD0
BRT+ -> / 22 Package QFP-80 61 / <- VCESEL
B-Y- <> / 23 60 / ?? TEST3
B-YC <> / 24 59 / <- TEST2 (YUV HI/LO)
/ 58 / <- TEST1 (PAL/YUV)
\ 57 / -- +5V (D)
GND (A) -- \ 25 56 / -- GND (D) Orientation:
B-Y <- \ 26 55 / -- GND (D) --------------------
+5V (A) -- \ 27 54 / -- +5V (D) 64 41
B-Y+ -> \ 28 53 / -- +5V (D) | |
GND (A) -- \ 29 52 / <- RGB+ .-----------.
R-Y- <> \ 30 51 / -> B 65-| O|-40
R-YC <> \ 31 50 / -- +5V (A) | HuC6260|
GND (A) -- \ 32 49 / -> R 80-|O HUDSON |-25
R-Y <- \ 33 48 / -- GND (A) '-----------'
+5V (A) -- \ 34 47 / -> G | |
R-Y+ -> \ 35 46 / <> RGB- 01 24
+5V (A) -- \ 36 45 / <- SYN+
Y- <> \ 37 O 44 / -> SYNC Legend:
YC <> \ 38 43 / <> SYN- ----------------------------
GND (A) -- \ 39 42 / <- Y+ --[HuC6260]-- Power, n/a
Y <- \ 40 41 / -- +5V (A) ->[HuC6260]<- HuC6260 input
\ / <-[HuC6260]-> HuC6260 output
\ / <>[HuC6260]<> Bidirectional
\ / ??[HuC6260]?? Unknown
V
== Signal descriptions ==
* '''+5V (A)''', '''GND (A)''': Power for analog signals.
* '''+5V (D)''', '''GND (D)''': Power for digital signals.
* '''OSC''': 21.4772 MHz clock input.
* '''CK''': Output clock for the VDC, configured by the CPU.
* '''/CS''': Chip select. Connected to CPU CEK, selecting the VDC when writing to $FF:$0400-$07FF.
* '''8/16''': Controls CPU data bus width. This is connected to +5V (8-bit mode).
* '''CPU D8''': Used in 16-bit mode. However, the PC-Engine uses 8-bit mode exclusively, so this is not connected.
* '''VD8..VD0''': 9-bit color input from the VDC. VD8 is connected to the VDC's SPBG output.
* '''/HSYN''', '''/VSYN''': Horizontal and vertical sync for the VDC, to which the VDC synchronizes its video output.
* '''VCESEL''': 'Output Control' or 'Video Select'. Deasserting makes /HSYN, /VSYN, and CK go high impedance, freezing output from the VDC, but the VCE still draws VD8..0 input as normal. Connected to the expansion port (along with /HSYN, /VSYN, and CK), but normally floating externally. Can be used to control the VDC from an expansion port video device instead of the VCE.
* '''TEST1''' ('''PAL/YUV'''): When grounded, reading palette RAM returns data from the YUV ROM, instead. The YUV ROM is indexed using the value at the palette RAM address being read by the CPU. This pin is normally not connected.<ref name="yuv">[http://furrtek.free.fr/?a=pceyuv furrtek]: Dumping the NEC PC Engine YUV table</ref>
* '''TEST2''' ('''YUV HI/LO'''): Controls which half of the 15-bit YUV value is returned to the CPU when reading from YUV ROM. When reading the high byte, bit 7 is always 0. This pin is normally not connected.<ref name="yuv" />
* '''TEST3''': This appears to have a function, but its behavior is unknown. Normally not connected.
Note: Pins appear to be pulled up internally, so not connected pins are high.
== References ==
<references />
a1d49285d99291fa270bb313f501cefc7fc90f3b